The present invention relates generally to semiconductor devices and, more particularly, to a semiconductor device with a conductive via and a method of making the same.
Spurred by demand for smaller and faster devices, the semiconductor industry continues to reduce the feature size in integrated circuits (ICs). Interconnect architecture in ICs currently includes metal stacks and spaces less than 0.4 .mu.m wide. In an IC with a multilevel metallization scheme, the various metal levels are typically connected by conductive vias that are formed by filling via holes with tungsten. One complicating factor in the design of ICs having reduced feature size is that the diameter of the conductive vias must be kept relatively large for two reasons. The first reason is to limit the conductive via resistance, which increases inversely with the square of the diameter of the conductive via. The second reason is to limit the aspect ratio (AR) of the via hole so that an adequate glue layer can be formed on surfaces within the via hole. In the case of a via hole less than 0.25 .mu.m in diameter, it is difficult to form an adequate glue layer, which is needed to facilitate filling of the via hole with tungsten, if the AR of the via hole exceeds about 3:1.
In some recent IC designs the objective of reducing feature size while keeping the diameter of the conductive vias relatively large has been achieved by tolerating misalignment of the conductive via with one or both of the metal stacks above and below the conductive via. In the case where the conductive via is misaligned with the bottom metal stack, a portion of the conductive via "falls off" the edge of the metal stack and produces a deep recess in the dielectric material adjacent to the sidewall of the metal stack. This deep recess occurs during dry plasma etching of the dielectric to form the via holes because a degree of overetching is required to ensure that all dielectric material is removed from the top of the metal stack and there is no etch stop in the region adjacent to the metal stack. Consequently, the required overetching removes dielectric material in the region adjacent to the metal stack. A conductive via that is misaligned with the bottom metal stack is sometimes referred to as an "unlanded" conductive via and the high aspect ratio region, i.e., the deep recess, adjacent to the sidewall of the metal stack is sometimes referred to as the "unlanded" region.
One problem with unlanded conductive vias is that they expose the sidewall of the metal stack and thereby render the metal stack susceptible to attack during chemical vapor deposition (CVD) of tungsten used to fill the via holes. Attempts have been made to provide a barrier layer that protects the sidewall of the metal stack. For example, in one conventional process flow, after the via holes are etched, a barrier layer, e.g., 50 angstroms to 500 angstroms of Ti/TiN, is first deposited by a standard physical vapor deposition (PVD) or CVD technique and then the via holes are filled with tungsten by CVD. In the case of an unlanded conductive via, such a barrier layer covering the sidewall of the metal stack is effective only if it is continuous and has sufficient thickness and density to resist penetration of WF.sub.6, which is the tungsten source gas typically used in the tungsten CVD fill process. If the barrier layer does not resist penetration by WF.sub.6, then any exposed metal in the stack that reacts with WF.sub.6, e.g., titanium and aluminum, will be attacked thereby causing the formation of a high resistance interface layer that may lead to conductive via failure.
FIG. 1A illustrates at 100 a portion of a semiconductor device in which an unlanded conductive via has caused a sidewall of a metal stack to be attacked during the tungsten CVD fill process. As shown in FIG. 1 A, semiconductor substrate 102 has dielectric layer 104 disposed thereover. Metal stacks 106 are disposed on a first level over dielectric layer 104. Dielectric layer 108 disposed over metal stacks 106 has conductive vias 110 formed therein. Metal stacks 112a and 112b are disposed on a second level over dielectric layer 108. Conductive vias electrically connect metal stacks 106 and 112a. As shown in FIG. 1A, conductive vias 110 are misaligned with respect to metal stacks 106 and therefore constitute unlanded conductive vias, as discussed above. Conductive vias 110 are also misaligned with respect to metal stacks 112a.
FIG. 1B shows an enlarged view of region 114 indicated by the dashed circle in FIG. 1A. As shown in FIG. 1B, metal stack 106 includes layers 116, 118, 120, and 122. A wetting layer 116 formed of, e.g., Ti or TiN, is disposed over dielectric layer 104. Aluminum layer 118 is disposed over barrier layer 116. Titanium layer 120 is disposed over aluminum layer 118. Titanium nitride layer 122 is disposed over titanium layer 120. Contaminated regions 124 in titanium layer 120 are produced when WF.sub.6 attacks the sidewall of layer 120, which is adjacent to the unlanded region of conductive via 110. The reaction between WF.sub.6 and titanium produces a number of reaction products including TiF.sub.3, TiF.sub.4, and certain tungsten-containing materials. The production of TiF.sub.3, which is a gas, consumes solid titanium and thereby causes voids to be formed in titanium layer 120 as WF.sub.6 advances into layer 120. The production of TiF.sub.3 is further problematic because any such gas trapped within titanium layer 120 generates stress that may lead to delamination of titanium nitride layer 122. The production of TiF.sub.4, or other fluorine- or tungsten-containing compounds having high resistance, creates a high resistance interface layer that may cause conductive via failure. Although not indicated as such in FIG. 1B for the sake of clarity, any exposed portion of the sidewall of aluminum layer 118 also may be attacked by WF.sub.6. The degree to which aluminum layer 118 is attacked is less than that of titanium layer 120; however, due to the relatively lower reactivity of aluminum with WF.sub.6.
To date, barrier layers formed by standard PVD techniques have not been effective to protect the sidewall of a metal stack from being attacked during the tungsten CVD fill process. A barrier layer of TiN formed by CVD provides adequate step coverage in the unlanded region; however, this approach presents significant reliability issues because of particle contamination and the poor TiN film properties produced by the CVD process. Another approach involves deposition of a TiN barrier layer by metalorganic chemical vapor deposition (MOCVD) followed by N.sub.2 /H.sub.2 plasma treatment. This MOCVD approach is undesirable because the subsequent plasma treatment does not burn off all the organic components, particularly at the sidewalls of the via hole and in the unlanded region, which results in the barrier layer being too weak in those areas to resist penetration by WF.sub.6. Yet another approach involves deposition of a TiN barrier layer by an ionized sputter (PVD) technique, e.g., ionized metal plasma (IMP). This approach does not protect the sidewall of the metal stack because little or no deposition of IMP TiN occurs in the unlanded region. As such, the exposed portion of the sidewall of the metal stack, which contains free titanium, remains exposed after deposition of the barrier layer and, consequently, can be easily attacked by WF.sub.6.
Protection of the sidewalls of a metal stack is also a concern in so-called self-aligned vias in which silicon nitride spacers cover the sidewalls of the metal stack. For example, the via etch can etch through the spacers if adequate selectivity of the oxide etch to silicon nitride is not maintained. The spacers also can be attacked when exposed to solvents during post-etch stripping. As such, the presence of such silicon nitride spacers does not ensure that the sidewalls of a metal stack are adequately protected from being attacked during the tungsten CVD fill process. Furthermore, the presence of silicon nitride spacers, which are relatively thick, between metal stacks is undesirable because silicon nitride has a relatively high dielectric constant and therefore slows down interconnect speed.
In view of the foregoing, there is a need for a reliable method of protecting the sidewall of a metal stack from being attacked by WF.sub.6, during the tungsten CVD fill process used in the production of unlanded conductive vias.